By D. Crawley, K. Nikolic, M. Forshaw
It truly is changing into more and more transparent that the two-dimensional format of units on laptop chips is beginning to prevent the improvement of high-performance desktops. third-dimensional buildings can be had to give you the functionality required to enforce computationally extensive projects. 3-D Nanoelectronic machine structure and Implementation experiences the cutting-edge in nanoelectronic gadget layout and fabrication and discusses the architectural elements of 3D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. this can be a important reference for these all in favour of the layout and improvement of nanoelectronic units and expertise.
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Extra resources for 3D Nanoelectronic Computer Architecture and Implementation (Series in Materials Science and Engineering)
4. 3 are very likely to have some crosstalk between the vertical interconnections. Therefore, the results from this technique provide a useful ‘benchmark’ for comparison with other techniques in which the conduction is anisotropic. Metallic connections may also be used and a number of different techniques have been developed. 5. Here, it is not possible to distinguish a vertical interconnection ‘layer’. Because the vertical connections are formed by metal deposition into deep trenches, they can be considered as extended vias which also connect the stacked chips.
Through-chip vias are described in detail in chapter 11. The vertical interconnections may take many forms, including ‘molecular wires’ formed using the polymer and discotic liquid crystal techniques described in chapters 9 and 8. 4. 3 are very likely to have some crosstalk between the vertical interconnections. Therefore, the results from this technique provide a useful ‘benchmark’ for comparison with other techniques in which the conduction is anisotropic. Metallic connections may also be used and a number of different techniques have been developed.
Using this technique, the authors claim that a power dissipation of between 80 and 100 W could be achieved with a cubic volume of about 16 cm3 (at a peak temperature of around 73 ◦C). This would imply a stack of about 50 layers of active devices. It should be noted that, in this work, the connections between layers were made on one face of the cube. 8. Structures studied by Yamaji et al  An alternative possibility might be to use active device layers of isotopically enriched or purified silicon.
3D Nanoelectronic Computer Architecture and Implementation (Series in Materials Science and Engineering) by D. Crawley, K. Nikolic, M. Forshaw