By Aida Todri-Sanial, Jean Dijon, Antonio Maffucci
This ebook presents a single-source reference at the use of carbon nanotubes (CNTs) as interconnect fabric for horizontal, on-chip and 3D interconnects. The authors reveal the makes use of of bundles of CNTs, as cutting edge carrying out fabric to manufacture interconnect through-silicon vias (TSVs), with the intention to enhance the functionality, reliability and integration of 3D built-in circuits (ICs). This booklet may be first to supply a coherent assessment of exploiting carbon nanotubes for 3D interconnects overlaying features from processing, modeling, simulation, characterization and purposes. assurance additionally incorporates a thorough presentation of the appliance of CNTs as horizontal on-chip interconnects that could probably revolutionize the nanoelectronics undefined. This publication is a must-read for a person drawn to the cutting-edge on exploiting carbon nanotubes for interconnects for either second and 3D built-in circuits.
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Additional info for Carbon Nanotubes for Interconnects: Process, Design and Applications
TDDB performance can be improved by minimizing electric field enhancement. Considering that the minimum feature size on the die will continue to shrink in accordance with Moore’s law at future technology generations, the only way to achieve this is by optimizing the manufacturing processes and ensuring that the dimensions are perfectly controlled with minimal roughness on the edges of the interconnect structures and minimal misalignment between the vias and the upper or lower metal layers. Overcoming the inherent critical dimension and overlay variation associated with multiple patterning technologies using 193 nm lithography tools is a challenging task at ultra-scaled dimensions.
Naeemi A, Meindl J (2007) Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems. IEEE Trans Electron Devices 54:26–37 14. Naeemi A, Meindl J (2009) Compact physics-based circuit models for graphene nanoribbon interconnects. IEEE Trans Electron Devices 56:1822–1833 15. Nathanael R, Pott V, Kam H, Jeon J, Liu T-J (2009) 4-Terminal relay technology for complementary logic. In: IEDM Technical Digest, pp 1–4 16.
The time delay dominated by resistance and capacitance (R and C) will increase [11, 25]. 0 ps and RC delay of a 1 mm length of Cu wire can be 250 ps . Moreover, the higher resistivity as well as longer interconnect length and higher current density due to reduction of dimension  will also make wire voltage-drop more significant, leading to an obviously increase in power consumption. 13 m technology node, and up to 80 % of power can be consumed by interconnect at 45 nm node . Furthermore, the dimension reduction of Cu interconnect may shorten the EM failure time .
Carbon Nanotubes for Interconnects: Process, Design and Applications by Aida Todri-Sanial, Jean Dijon, Antonio Maffucci