By Kunle Olukotun
Chip multiprocessors - also referred to as multi-core microprocessors or CMPs for brief - are actually the single method to construct high-performance microprocessors, for quite a few purposes. huge uniprocessors are not any longer scaling in functionality, since it is simply attainable to extract a constrained volume of parallelism from a standard guideline flow utilizing traditional superscalar guide factor suggestions. furthermore, one can't easily ratchet up the clock pace on state-of-the-art processors, or the facility dissipation turns into prohibitive in all yet water-cooled platforms. Compounding those difficulties is the easy undeniable fact that with the big numbers of transistors on hand on cutting-edge microprocessor chips, it really is too high priced to layout and debug ever-larger processors each year or . CMPs keep away from those difficulties by means of filling up a processor die with a number of, quite less complicated processor cores rather than only one large center. the precise measurement of a CMPs cores can fluctuate from extremely simple pipelines to reasonably complicated superscalar processors, yet as soon as a middle has been chosen the CMPs functionality can simply scale throughout silicon strategy generations just by stamping down extra copies of the hard-to-design, high-speed processor middle in each one successive chip iteration. furthermore, parallel code execution, acquired by means of spreading a number of threads of execution around the a variety of cores, can in attaining considerably greater functionality than will be attainable utilizing just a unmarried middle. whereas parallel threads are already universal in lots of beneficial workloads, there are nonetheless vital workloads which are difficult to divide into parallel threads. The low inter-processor verbal exchange latency among the cores in a CMP is helping make a much broader diversity of purposes attainable applicants for parallel execution than used to be attainable with traditional, multi-chip multiprocessors; however, constrained parallelism in key functions is the most issue restricting popularity of CMPs in a few sorts of platforms.
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Extra info for Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Going forward, future Niagara processors will likely include more threads per chip and support multiple chips in a single shared-memory system, leading to a very large number of active threads switched by hardware even in small, cost-effective systems. While many commercial applications have sufficient parallelism to be able to scale to several hundreds of threads, applications with more limited scalability will only be able to use a fraction of the threads in a future Niagara system. Of course, workloads consisting of many of these more limited scalability applications can be multiprogrammed on Niagara systems under control of the operating system.
2 commercial database server. The first was an OLTP workload modeled after the TPC-B benchmark . This benchmark models a banking database system that keeps track of customers’ account balances, as well as balances per branch and teller. Each transaction updates a randomly chosen account balance, which includes updating the balance of the branch the customer belongs to and the teller from which the transaction is submitted. It also adds an entry to the history table, which keeps a record of all submitted transactions.
In addition, Niagara, along with many of the more recent processors, has hardware support for virtualization, and multiple operating systems (each referred to as a “guest” OS) can be run on a single Niagara system, with each guest operating system running their own set of application workloads. As single systems become capable of running what used to require multiple dedicated mainframes, this ability to consolidate multiple workloads, each book Mobk089 48 October 26, 2007 10:22 CHIP MULTIPROCESSOR ARCHITECTURE running under their own guest operating system, fully protected from the effects of other guest operating systems, will become extremely important.
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency by Kunle Olukotun