By Harry Veendrick
These days, CMOS applied sciences account for nearly ninety% of all built-in circuits (ICs). This e-book offers a necessary creation to CMOS ICs. The contents of this booklet are established upon a past ebook, entitled 'MOS Ics', which was once released in Dutch and English by means of Delta Press (Amerongen, The Netherlands, 1990) and VCH (Weinheim, Germany, 1992), respectively.
This publication includes cutting-edge fabric, but in addition makes a speciality of facets of scaling as much as and past 0.1 mm CMOS applied sciences and designs. It sincerely describes the elemental CMOS working rules and provides vast perception into numerous elements of layout, implementation and alertness. unlike different works on this subject, the e-book explores all linked disciplines of deep-submicron CMOS ICs, together with physics, layout, know-how and packaging, low-power layout and sign integrity. The textual content relies upon in-house Philips courseware, which, to this point, has been accomplished via greater than 1500 engineers. rigorously established and enriched through countless numbers of figures, photograhs and in-depth routines, the publication is well-suited for the aim of self-study.
This moment variation includes a few corrections and is totally up-to-date with admire to the former one. within the one-and-a-half years of its existance, the 1st variation has already been utilized in greater than ten in-house classes. numerous typing blunders and so forth, which confirmed up in the course of those classes, were corrected. additionally, many of the chapters were up to date with cutting-edge fabric. Numbers that describe developments and roadmaps were up to date besides, to allow the contents of this ebook be necessary for a minimum of one other 5 years.
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Extra resources for Deep-Submicron CMOS ICs - From Basics to ASICs (Second Edition)
1 Introduction. 2 Clock distribution and critical timing issues . . 3 Clock generation and synchronisation in different . 408 (clock) domains on a chip ..... . . . 4 Phenomena related to large current fluctuations . 5 The influence of the interconnection (metallisation . 426 and dielectrics) . . ............... 6 Design organisation . . 438 . 4 Conclusions. 438 . 5 References . 440 . 6 Exercises. 10 Testing, debugging, yield and packaging . 1 Introduction . 2 Testing ...................
1 Introduction . . . . . . 2 Design for reliability ........ . . . . . 1 Introduction ......... 2 Latch-up in CMOS circuits . . . . . . 3 Electrostatic discharge (ESD) and its protection . 390 . . . . . . 4 Electromigration ....... 5 Hot-carrier degradation . . . . . .. . 398 . . . . . . 3 Design for signal integrity . . . . . . 1 Introduction. 2 Clock distribution and critical timing issues . . 3 Clock generation and synchronisation in different . 408 (clock) domains on a chip .....
Depletion or normally-on transistors: Current flows through a depletion transistor when Vgs = . VT < 0 for an nMOS depletion transistor and VT > 0 for a pMOS depletion transistor. 8 Parasitic MOS transistors MOS (V)LSI circuits comprise many closely-packed transistors. 22. 22: Example of a parasiticMOS transistor Transistors T1 and T 2 are separated by the field oxide. Parasitic MOS transistor T3 is formed by an interconnection on the field oxide and the n+ areas of transistors T1 and T2 . This field oxide is thick in comparison with the gate oxide, which ensures that the threshold voltage VTpar of transistor T 3 is larger than the threshold voltages of transistors T1 and T 2 .
Deep-Submicron CMOS ICs - From Basics to ASICs (Second Edition) by Harry Veendrick