Download Designing TSVs for 3D Integrated Circuits by Nauman Khan PDF

By Nauman Khan

ISBN-10: 1461455073

ISBN-13: 9781461455073

This ebook explores the demanding situations and offers top innovations for designing Through-Silicon Vias (TSVs) for 3D built-in circuits.  It describes a singular strategy to mitigate TSV-induced noise, the GND Plug, that's enhanced to others tailored from 2-D planar applied sciences, akin to a bottom flooring aircraft and standard substrate contacts. The publication additionally investigates, within the kind of a comparative research, the influence of TSV measurement and granularity, spacing of C4 connectors, off-chip strength supply community, shared and devoted TSVs, and coaxial TSVs at the caliber of energy supply in 3-D ICs. The authors supply specific top layout practices for designing three-D energy supply networks.  due to the fact that TSVs occupy silicon real-estate and effect equipment density, this booklet presents 4 iterative algorithms to lessen the variety of TSVs in an influence supply community. not like different latest equipment, those algorithms could be utilized in early layout levels whilst merely practical block- point behaviors and a floorplan can be found. eventually, the authors discover using Carbon Nanotubes for energy grid layout as a futuristic replacement to Copper.

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Additional resources for Designing TSVs for 3D Integrated Circuits

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This insulating material helps to reduce TSV-induced substrate noise but deteriorates TSV performance to extract heat from substrate. A model of thermal TSV without liner is, thus, not accurate and none of the previous models of thermal TSV include liner. Mechanical stress associated with TSV calls for a keep-away area where no devices can be fabricated. Therefore TSVs cannot be directly connected to a hotspot or any floorplan tile as assumed in [120]. Power TSVs connect to only the top metal layers.

5 summarizes the above presented three studies to evaluate the potential benefit of using coaxial TSV for 3-D PDN. The first column shows the technique used to integrate coaxial TSV into the 3-D PDN. The next three columns quantify three parameters (number of blockages, size of each blockage, and the number of additional signal routes) that we use to compare the implementations. The last column summarizes the main benefit obtained from each integration technique. Clearly, coaxial TSVs present an exciting opportunity to reduce the number of blockages, integrate extra decoupling capacitance, and provide additional signal routes.

0 1 magnitude when compared to using thicker liner and backside ground approaches. For the design parameters, shown in Fig. 5 μm2 . 5 μm and an aspect ratio of 40:1 is achievable. 2. These results show that even the smaller aspect ratio yields 40% reduction in TSV-induced noise when compared to the other two approaches. If the desired substrate noise limit is 10% of VDD, then the GND plug with a height of 20 μm is the only solution that safely enables placing a device 6 μm from the TSV center. The resulting keep out zone considering TSV-induced noise is thus a square area of side 5 μm.

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Designing TSVs for 3D Integrated Circuits by Nauman Khan

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